Referring to FIG. 1, a cross sectional view of a conventional MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 includes a drain region 102, a source region 104, and a channel region 106 fabricated within a semiconductor substrate 108, as known to one of ordinary skill in the art of electronics. A gate dielectric 110 is disposed over the channel region 106 of the MOSFET 100. The MOSFET 100 also includes a gate comprised of polysilicon 112 disposed over the gate dielectric 110. Spacer structures 113 typically formed of an insulating material surround the gate dielectric 110 and the gate structure over the gate dielectric 110, as known to one of ordinary skill in the art of electronics.
For making contact to the drain region 102, the source region 104, and the polysilicon 112 of the gate, a metal silicide is formed on the drain region 102, the source region 104, and the polysilicon 112 of the gate. A drain silicide 114 is formed on the drain region 102, a source silicide 116 is formed on the source region 104, and a gate silicide 118 is formed on the polysilicon 112 of the gate of the MOSFET 100.
For efficiency in fabrication, the drain silicide 114, the source silicide 116, and the gate silicide 118 are typically fabricated simultaneously in the prior art. During the fabrication of the suicides, the drain region 102, the source region 104, and the polysilicon 112 are exposed, and metal is deposited on those regions. Then, a silicidation anneal is performed, and the drain silicide 114, the source silicide 116, and the gate silicide 118 form from a reaction of the deposited metal with silicon during the silicidation anneal.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, as the dimensions of the MOSFET 100 are scaled down, the depth of diffusion of the drain region 102 and the source region 104 into the semiconductor substrate 108 and the thickness of the polysilicon 112 of the gate are scaled down. Thus, the depth of the drain silicide 114 and the source silicide 116 and the thickness of the gate silicide 118 are also scaled down.
However, such scaling down of the thickness of the gate silicide 118 results in higher resistivity of the gate of the MOSFET 100. Such higher resistivity in turn leads to slower device speed of the MOSFET 100. Nevertheless, scaling down the dimensions of the MOSFET 100 is also advantageous.
Thus, a method is desired for fabricating a gate with low resistivity within such a MOSFET with scaled down dimensions.